Intel Enters High-Volume Manufacturing with High-NA EUV on 18A Node
Intel and ASML have transitioned 0.55 NA High-NA EUV lithography into high-volume manufacturing, dual-qualifying critical layers on 18A-based Panther Lake notebook processors. While the technology reduces multi-patterning steps and defects, it introduces anamorphic lens stitching challenges and a 2.5x exposure cost premium over conventional 0.33 NA systems.
High-NA EUV Integration on the 18A Node
Intel Foundry has initiated high-volume manufacturing using ASML's 0.55 Numerical Aperture (High-NA) EUV lithography scanners. Rather than waiting for future nodes, Intel has integrated the $380 million tool to print a subset of layers for its Panther Lake notebook processors (Core Ultra Series 3). These chips are fabricated on the Intel 18A process, which was natively designed around conventional 0.33 NA Low-NA EUV and multi-patterning.
To mitigate risks, Intel dual-qualified these target layers to run on both Low-NA and High-NA tools at its D1X facility in Hillsboro, Oregon. This parallel qualification path ensures that Panther Lake yields on the High-NA tools match those of the mature Low-NA systems. Integrating High-NA into 18A serves as a low-risk, operational learning phase, establishing process recipes and tool familiarity ahead of the 14A and 10A nodes where High-NA exposure becomes a design requirement.
Optics, Field Size Halving, and Reticle Stitching
The transition from 0.33 NA to 0.55 NA EUV sharpens the smallest single-exposure features by roughly one-third by widening the light cone gathered by the optics. This shift allows fabs to print complex designs in a single exposure pass, replacing the multi-patterning schemes (double or triple exposures) required by Low-NA systems. Eliminating exposure passes directly reduces mask count, cycle times, and alignment-induced defect opportunities.
However, achieving a 0.55 NA required ASML to implement anamorphic optics, which magnify the mask differently along the X and Y axes. This design modification halves the exposure field size from the standard 858 mm² (26 x 33 mm) down to 429 mm² (26 x 16.5 mm). Consequently, full-reticle dies must be exposed in two separate halves and stitched together. To address the resulting throughput and alignment penalties, ASML's production-grade EXE:5200B scanner employs a 6-by-12-inch mask to reduce stitching overhead, achieving a throughput of 175 wafers per hour at a 0.7 nm overlay.
Economic Realities and Foundry Roadmap Divergence
The primary hurdle for widespread High-NA adoption is cost. Industry analysis indicates that a single High-NA exposure costs approximately 2.5 times more than a Low-NA exposure. This premium means High-NA only becomes economically viable when a single pass replaces three or more Low-NA masks—a crossover point projected around 2030. Additionally, printing smaller geometries requires a higher EUV dose, which increases scanner dwell time and threatens wafer-per-hour economics.
This fiscal reality has driven a sharp strategic divergence between leading foundries:
- Intel has adopted an aggressive posture, aiming to secure first-mover advantages for its 14A node.
- TSMC has taken a conservative path, skipping High-NA for its 2nm and A16 nodes, and remaining non-committal through 2029.
- Memory manufacturers and research consortia are also scaling up, with SK Hynix installing its first commercial system in late 2025, alongside orders from Samsung and IBM.
ASML is currently producing 12 to 15 High-NA systems annually, with plans to scale to approximately 20 systems per year by 2028.